library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;

entity fenlu is
	port (
		DATA : in std_logic_vector(47 downto 0);
		sel  : in std_logic_vector(1 downto 0);
		result0: out std_logic_vector(47 downto 0);
		result1: out std_logic_vector(47 downto 0);
		result2: out std_logic_vector(47 downto 0);
		result3: out std_logic_vector(47 downto 0));
end fenlu;

architecture RTL of fenlu is

begin
	process(sel, DATA)
	begin
		if (sel="00") then
			result0 <= DATA;
			result1 <= (others => '0');
			result2 <= (others => '0');
			result3 <= (others => '0');
		elsif (sel="01") then
			result0 <= (others => '0');
			result1 <= DATA;
			result2 <= (others => '0');
			result3 <= (others => '0'); 
		elsif (sel="10") then
			result0 <= (others => '0');
			result1 <= (others => '0'); 
			result2 <= DATA;
			result3 <= (others => '0'); 
		elsif (sel="11") then
			result0 <= (others => '0');
			result1 <= (others => '0'); 
			result2 <= (others => '0');
			result3 <= DATA;
		end if;
 	end process;
end RTL;